An integrated circuit device such as an ASIC device, which incorporates RAM or other memory macros in addition to logic circuitry, is required to test the access time and other AC characteristics of an internal RAM macro with good precision. Because these measurements are performed using external testing equipment, it has been proposed that flip-flops be placed in the input stage and output stage of a RAM macro, so that a control clock pulse is input to the RAM macro from the input stage flip-flop in response to a first clock pulse, and that the output from the RAM macro be captured by the output stage flip-flop on the second control clock pulse.
FIG. 1 shows a method of the prior art for RAM macro measurement. A first flip-flop 12 is provided in the input stage of the RAM macro 14 incorporated into the integrated circuit device 10, and a second flip-flop 16 is provided in the output stage; an input signal S12 from an external testing device 18 is captured by the first flip-flop 12 with the timing of the first clock S1, and a control clock pulse CLKt is input to the RAM macro 14. Further, the RAM macro data output Dout is captured by the second flip-flop 16 with the timing of a second clock S2 and is supplied to the external testing device 18. By varying the timing of the second clock S2 with reference to the first clock S1 to determine the timing at which the correct data output Dout can be obtained, the access time of the RAM macro 14 is measured.
A RAM macro begins a read operation in sync with the control clock CLKt, and after a prescribed access time outputs the read-out data output Dout. By selecting the address Add such that the read-out data changes from H level to L level, or from L level to H level, the output timing of the data output Dout can be detected.
Further, in for example Japanese Patent Laid-open No. 2001-208804, a technique is proposed in which a circuit which generates the above first clock Si and second clock S2 is incorporated within the integrated circuit device, and similar measurements are performed while modifying the timing of the second clock S2 through an incorporated variable delay control circuit.
However, when using the method of measuring the time delay between flip-flops provided before and after the RAM macro, due to such factors as the precision with which the test device control clocks Si and S2 are generated, the difference in delay times of the flip-flops corresponding to the control clocks Si, S2, and the precision of operation of the flip-flops themselves, an error of order several hundreds of picoseconds occurs in the measured value. The access time for SRAM and other high-speed RAM may for example be 1 nsec or so, and so the above measurement error is too large to be ignored.
Hence an object of this invention is to provide an integrated circuit device having an internal test circuit capable of performing precise measurements of the AC characteristics of an internal RAM macro.
A further object of this invention is to provide an integrated circuit device having an internal test circuit capable of precise measurement of the clock access time of internal RAM, and of precise measurement of the pulse width of control pulses (or of the control clock) and of the characteristic values of the setup time and hold time for control pulses (or the control clock).